Memory devices are now present in virtually every computing device found in home and business settings. Personal computers, workstations, servers and other computer systems, for example, typically use random access memory (RAM) devices to store data and instructions to be executed by the computer. Although various forms of digital memory devices have been in use for several decades, engineers are continually looking for opportunities for improvement in terms of increasing the speed with which data can be accessed, reducing the size of the memory device, reducing the amount of electrical power consumed by the device, or the like.
One type of memory device that is presently in common use is the dynamic random access memory (DRAM). DRAMs use large arrays of capacitive elements to store electrical signals representing binary digits (“bits”) of information. FIG. 1 is a conceptual block diagram of a conventional DRAM. With reference now to FIG. 1, a memory bank 102 suitably includes a large number of capacitive elements conceptually arranged in a grid pattern. Each capacitive element is typically addressable by a row address and a column address representing the location of a cell within the memory bank 102.
A central processing unit (CPU) or other computing component typically references a memory cell by providing the cell's address to the memory device via an address bus 104 made up of several (typically 2–16) electrical conductors called “address lines”. Address bus 104 typically transports row and column addresses that correspond to individual memory cells within memory bank 102 in which data may be stored or retrieved. Addresses transmitted on address bus 104 are typically received and initially stored in a column address latch 106 and/or a row address latch 110, as appropriate, prior to processing by memory device 100. Control signals such as row address strobe (/RAS) and column address strobe (/CAS) signals are provided from a controller (not shown in FIG. 1) to latch the row and column addresses, respectively, to a row decoder 112 and a column decoder 108. The /CAS and /RAS signals are frequently described with a preceding “/” to indicate that these signals are typically enabled when they are in a low voltage logic state.
Decoders 112 and 108 suitably decode the row and column addresses, respectively, to access the appropriate cell in memory bank 102. The controller typically also provides a write enable (/WE) signal that is active when data is being written to the cell. The /WE signal is typically deactivated when data is being read from the cell.
Data stored within each DRAM cell is conventionally represented as a logic “0” or a logic “1” corresponding to low and high voltages, respectively, stored in the capacitive element. Because the charge stored within a capacitor typically degrades over time, the capacitors typically need to be refreshed relatively frequently. Memory device 100 therefore includes amplifiers 114 to refresh the electrical signals contained within each node capacitor in memory bank 102, and to transfer data between memory bank 102 and data bus 116.
With continuing reference to FIG. 1, an exemplary process in a conventional DRAM read process suitably begins with a processor or CPU placing a row address for data to be retrieved on address bus 104. The row address is received on address pins in the memory device 100, and the address is stored in row address latch 110 when the /RAS pin becomes active. Row address decoder 112 then selects the row to be accessed. With the write enable (/WE, not shown) disabled, the column address desired by the processor CPU is placed on address bus 104. This address is stored within column address latch 106 until the /CAS signal becomes active, at which time the column address is provided to column address decoder 108. A combination of control signals such as /RAS, /CAS and /WE signals are suitably decoded to enable the output for data interface 114 to retrieve the identified data in memory bank 102 and to provide the data on data bus 116. A combination of control signals such as /RAS, /CAS and /WE signals may be subsequently used to issue a precharge to the device. During this precharge period, data cannot typically be stored or retrieved in memory bank 102. A conventional DRAM write process executes similar steps as the read process described above in selecting an address to receive data from data bus 116.
In more recent years, synchronous dynamic random access memory (SDRAM) has become increasingly popular. SDRAMs typically combine multiple banks of memory elements onto a single module for additional data storage. SDRAMs are referred to as “synchronous” because they typically incorporate clock signals received from the host computer. An exemplary SDRAM memory device is described in U.S. Pat. No. 6,215,709, “Synchronous Dynamic Random Access Memory Device” which issued on Apr. 10, 2001 and is incorporated herein by reference in its entirety. A number of advanced techniques have been incorporated into DRAMs and SDRAMs, including the “automatic precharge” which precharges the appropriate elements in the memory device without the need for an explicit instruction to the memory device. An example of a memory device incorporating automatic precharge techniques is described in U.S. Reissue Pat. No. Re35,750 entitled “Word Line Driver Circuit Having An Automatic Precharge Circuit” which issued on Mar. 24, 1998 and is incorporated herein by reference in its entirety.
A continuing challenge in designing new memory devices is to reduce the amount of electrical power consumed by such devices. This need is driven by, among other things, increasing miniaturization in computing devices such as notebook computers, personal digital assistants, cellular phones, and the like where battery power may be in limited supply. It is also driven by a desire to provide increasingly functional or fast memory devices that operate within electrical constraints that may be set by industry standards, or by computer or processor manufacturers. Accordingly, it is desirable to reduce the amount of electrical current consumed within a random access memory device. These and other aspects of the invention shall become more apparent when read in conjunction with the accompanying drawing figures and the attached detailed description of exemplary embodiments.